

/*
**************************************************************************************************************
File:         tb_ddr3.sv
Description:  Defines the testbench required for testing the DDR3 interface
Author     :  Rohit Kulkarni
              Aditya Joshi
**************************************************************************************************************
*/
`include "package.sv"

`define DEBUG 1
`define INPUTFILENAME "input_command.txt"		// filename for test data: one pair of short real operands/line

module tb_ddr3();
  reg CK = 0;
  reg command, rst; 
  reg [LOGICAL_ADDR_WIDTH-1:0] address;
  reg start;
  wire done; 
  reg OP;
  reg [LOGICAL_ADDR_WIDTH-1:0] ADDR;

  int data_file,scan_file,eof; 

  //top TOP(CK,rst,OP,ADDR,start,done);
  DDR_bus bus(.*);                                               //instantiate a DDR3 bus
  
  controller  DDR_controller(.IF(bus.memory_controller), .*);    //will use the mem_cntrl modport view

  DDR_memory  DDR_MEMORY(.IF(bus.memory_stub), .*);               //will use the mem_stub modport view
  
  bind controller ddr3_assertions ctrl_assert(.IF(IF));
  
initial
  begin
    forever #10 CK = ~CK;
  end

task drive_ddr3_inputs(reg command, reg [LOGICAL_ADDR_WIDTH-1:0] address);
  #5 rst = 1;
  #10 rst = 0;
  #10 OP = command;
  #1 ADDR = address;
  #1 start = 1;
  //#1 while(!done);
  @(posedge done) start = 0;
endtask


initial
	begin
	// open text file to read input number pair
	data_file = $fopen(`INPUTFILENAME, "r");
	eof = $feof(data_file);
	while(!eof)
	   begin
	     scan_file = $fscanf(data_file, "%b", command);
			 scan_file = $fscanf(data_file,"%h\n", address);
			 
			 eof = $feof(data_file);
			 
			 //call task
			 drive_ddr3_inputs(command,address);
			 
	   end

$fclose(data_file);
$stop;
end  
endmodule



